1. Field of the Invention
This invention relates to an SRAM memory array comprising memory cells with each cell containing seven devices, and in particular to a memory array wherein the basic storage nodes, which store the true and complement of the data, are constructed from six devices, forming a cross-coupled flip-flop cell. One internal storage node of this cell being connected to a separate read-pass device which passes the state of this node to a local bit line (LBL) for single-ended sensing, with the gate of this separate read-pass device connected to a separate read-word line.
2. Description of Background
Before our invention current six device SRAM cells were encountering significant stability problems as we scale below 0.1 micron. The main reason for this is that the device tolerances, particularly the threshold voltage variations from device to device, do not scale appropriately as the technology scales to smaller dimensions. When an SRAM cell is read, the bit lines are precharged ‘HIGH’ which places a ‘disturb’ signal on the ‘0’ node of the cross-coupled flip-flop. For the nominal design case, this ‘disturb’ signal is quite tolerable. However, if the threshold variations between devices is sufficiently large, this ‘disturb’ signal can cause some cells to flip state, i.e. a stored ‘0’ becomes a ‘1’ and vice versa. Current SRAM cell designs employ two techniques to circumvent this, 1) reduce threshold variations by making the devices, and hence cell, larger than the smallest size normal scaling rules would allow, and 2) use eight devices per cell, with the extra devices eliminating the ‘disturb’ signal during reading. Both techniques significantly increase the size of the SRAM cell and hence reduce the density, a very undesirable result.
A typical, 6T SRAM cell has two internal nodes, ‘A’ and ‘B’ one example of which is illustrated in prior art FIG. 1A which store ‘0’/‘1’ respectively on the two nodes for a stored ‘0’, and the reverse of ‘1’/‘0’ respectively on the nodes for a stored ‘1’. These two nodes are coupled to a pair of balanced bit/sense lines, which are used for both reading and writing. For reading the state of the cell, both bit lines are precharged ‘HIGH’ through a pass access device on each node (not shown). Subsequently, the word line of the selected row goes ‘HIGH’ and connects nodes ‘A’ and ‘B’ of this cell to the precharged bit lines through devices N2 and N3. As a result, within the cell, the internal storage node, which happens to currently be latched at ‘0’, will thus see a large voltage applied to it, which is the ‘disturb’ signal. If the difference in threshold voltages of the cross-coupled devices N1 and N2 is sufficiently large, this ‘disturb’ can cause the voltage on this ‘0’ node to rise sufficiently such that the cross-coupled arrangement will pull the previously ‘1’ node to ‘0’, thus reversing the stored state, a significant error.
One current method used to eliminate this read ‘disturb’ sensitivity is the use of an eight device SRAM cell one example of which is illustrated in prior art FIG. 1B. This adds two nFET devices, plus one read bit line and one read word line to each cell as illustrated by the encircled area 102. One of the storage nodes, for example node ‘B’ as illustrated, is connected to the gate of the pull down nFET device. This device has its source grounded and its drain in series with the read-select nFET. This read-select device has its drain tied to a separate read-bit line, while a separate read word line activates its gate. Thus each cell has the addition of two FET devices, plus one read bit line and one read word line.
For a given technology, the threshold variations between adjacent devices become larger as the devices approach minimum dimensions. Thus one method for improving stability is by making the device channel length and width larger, which results in lower density, an undesirable effect. If we wish to increase cell stability without increasing the cell device sizes, the bit line capacitance must be reduced without significantly increasing the effective, average cell size.